The disclosures herein relate generally to information handling systems (IHSs), and more specifically, to the duty cycle of clock signals that such IHSs may employ.
Information handling systems (IHSs) employ clock signals to control the timing of some of the components of such systems. Modern IHSs may require clock circuits that operate at very high speeds. The duty cycle of a clock signal refers to the amount of time a clock signal exhibits a first logic state, for example a logic high, versus the amount of time the clock signal exhibits a second logic state, for example a logic low. A clock signal exhibits a 50% duty cycle if the amount of time that the clock signal exhibits a first logic state is the same as the amount of time that the clock signal exhibits the second logic state. Duty cycle distortion is the variance that a particular clock signal exhibits from a desired duty cycle. Duty cycle distortion of clock signal may cause performance degradation in high speed IHSs.